features ? 1200v breakdown voltage ? low threshold, 1.6v max. ? high input impedance ? low input capacitance ? integrated high voltage resistor divider ? integrated 1000:1 resistor divider ? compact 3x3 lfga package applications ? high voltage shunt regulator ? high voltage linear amplifer ? high voltage digital pulsers ? high voltage sensing circuit general description the LN100 is a 1200v cascoded n-channel mosfet with an integrated high value high voltage resistor divider. multiple devices can be used in series for voltages greater than 1200v. a resistor divider ratio of 1000:1 is provided. high value resistors are used to minimize power consumption. the maximum gate-to-source threshold voltage is 1.6v. this allows the gate to be controlled by low voltage circuitry. the LN100 can be used as a high voltage low power pulser. it can also be used in a high voltage low current amplifer application where it is used to charge and discharge a small capacitive load. 1200v cascoded n-channel mosfet ordering information part number package option packing LN100la-g 6-lead lfga 3000/reel absolute maximum ratings parameter value drain-to-source voltage 1200v v 1 - v 2 differential voltage 1200v v 2 - v 3 differential voltage 5.0v operating temperature range -25c to +125c power dissipation, t a = 25c 350mw 1 absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied. continuous operation of the device at the absolute rating level may affect device reliability. all voltages are referenced to device ground. note: 1. device mounted on a 25mm x 25mm x 1.57mm board. pin confguration 6-lead lfga (top view) pads are at bottom of package. product marking 6-lead lfga package may or may not include the following marks: si or 6 v1 source 4 ga te 3 v3 2 v2 1 5 drain product summary bv dss min (v) r ds(on) max (k) i d(on) min (ma) 1200 3.0 3.0 l 100 y wll y = last digit of year sealed w = code for week sealed l = lot number = ?green? packaging typical thermal resistance package ja 6-lead lfga 186c/w esd sensitive device supertex inc. supertex inc. www .supertex.com LN100 doc.# dsfp-LN100 a031414
2 symbol parameter min typ max unit conditions mosfet m1 and m2 bv dss1 drain-to-source breakdown voltage of m1 600 - - v v gs = 0v, i d = 1.0a bv dss2 drain-to-source breakdown voltage of m2 600 - - v v gs = 0v, i d = 1.0a v gs(th) gate-to-source threshold voltage 0.5 - 1.6 v v gs = v ds , i d = 10a see test circuit r ds(on) static drain-to-source on-state resistance - - 3.0 k v gs = 2.8v, i d = 2.0ma see test circuit i d(on) on-state drain current 3.0 - - ma v gs = 2.8v, v ds = 25v see test circuit c iss input capacitance - - 50 pf v gs = 0v, v ds = 25v zener diode v z m2 gate-to-source zener diode clamp 6.5 - 12 v i gs = 1.0ma, v s = 0v i gs gate-to-source zener diode leakage - - 100 na v gs = 4.5v i z maximum zener current - 10 - ma --- resistors r 1 , r 2 , and r 3 r 1 + r 2 resistor divider r 1 + r 2 54 - - m v 1 = 0 to 1000v, v 2 = 0v r 1 resistor r 1 27 - - m v r1 = 0 to 500v r 2 resistor r 2 27 - - m v r2 = 0 to 500v r 3 resistor r 3 54 - - k v r3 = 0 to 5.0v r r 1 , r 2 , and r 3 matching - - 18 % --- electrical characteristics (t j = 25oc unless otherwise specifed) block diagram r 2 m1 m2 v1 v2 v3 gate source drain d r 1 r 3 LN100 supertex inc. www .supertex.com doc.# dsfp-LN100 a031414
3 drain-to-source on-resistance gate-to-source threshold voltage test circuits on-state drain current r 2 m1 m2 v1 v2 v3 gate so u rce d rain d ln 100 r 1 r 3 10v 10a v gs(th) r 2 m1 m2 v1 v2 v3 gate so u rce d rain d ln 100 r 1 r 3 10v 2.0ma v ds 2.8v r ds(on) = v ds 2.0ma r 2 m1 m2 v1 v2 v3 gate so u rce d rain d ln 100 r 1 r 3 2.8v 25v i d(on) LN100 supertex inc. www .supertex.com doc.# dsfp-LN100 a031414
4 high voltage, low current shunt regulator the LN100 can be used as a high voltage, low current shunt regulator as shown in figure 1. resistor divider r 1 , r 2 , and r 3 divides the output voltage by approximately 1000. v2 is the feedback voltage for the op-amp. if the reference voltage, v ref , is 1.0v, the output voltage will be shunted to 1000v. typical application circuits figure 1: high voltage, low current, shunt regulator figure 2: high voltage low current linear amplifer high voltage, low current linear amplifer in figure 2, the two LN100s are used as the main output stage for a 1000v low frequency amplifer to drive capacitive loads. the top LN100 is used to actively charge the load up to the desired voltage. the bottom LN100 is used to actively discharge the load to the desired voltage. the gate is driven with a low voltage op-amp. v 2 is the feedback voltage for the op-amp setting it to a gain of 60db. a 0 to 1.0v sinusoidal waveform on v in will create a 0 to 1000v sinusoidal waveform on hv out . output frequency only needs to go up to 300hz. c out hv out = 1000 x v in r 2 m1 m2 v1 v2 v3 gate so u rce d rain d ln 100 r 1 r 3 a + - v in c r 2 m1 m2 v1 v2 v3 gate so u rce d rain d ln 100 r 1 r 3 1000 v charge pump c out hv out = 1000 x v ref r 2 m1 m2 v1 v2 v3 gate so u rce d rain d ln 100 r 1 r 3 a + - v in LN100 supertex inc. www .supertex.com doc.# dsfp-LN100 a031414
5 typical application circuits (cont.) figure 3: high voltage low current 3000v digital pulser high voltage, low current digital pulser in figure 3, the six LN100s are used as the main output stage for a 3000v low frequency digital pulser. the frst three LN100s are used to charge the load up to 3000v. the next three LN100s are used to discharge the load back to ground. the integrated resistors in each of the LN100 allows the 3000v to be divided into thirds. each LN100 will only need to hold off 1000v. r 2 m1 m2 v1 v2 v3 gate so u rce d rain d ln 100 r 1 r 3 r 2 m1 m2 v1 v2 v3 gate so u rce d rain d ln 100 r 1 r 3 r 2 m1 m2 v1 v2 v3 gate so u rce d rain d ln 100 r 1 r 3 r 2 m1 m2 v1 v2 v3 gate so u rce d rain d ln 100 r 1 r 3 r 2 m1 m2 v1 v2 v3 gate so u rce d rain d ln 100 r 1 r 3 r 2 m1 m2 v1 v2 v3 gate so u rce d rain d ln 100 r 1 r 3 c c out hv out = 0 to 3000v v in = 0 to 3.0v hv = 3000v LN100 supertex inc. www .supertex.com doc.# dsfp-LN100 a031414
6 (the package drawings in this data sheet may not refect the most current specifcations. for the latest package outline information go to http://www.supertex.com/packaging.html .) 6-lead lfga package outline (la) 3.00x3.00mm body, 0.85mm height (max), 0.65mm pitch symbol a b d e d1 d2 e dimension (mm) min 0.75 0.30 2.925 2.925 0.225 2.00 bsc 0.65 bsc nom 0.80 0.35 3.000 3.000 0.325 max 0.85 0.40 3.075 3.075 0.425 drawings not to scale supertex doc. #: dspd-6lfgala3x3p065 , version a110811 seating plane t op vi ew side v iew bottom v iew a d e e b note 1 (index area d/2 x e/2) 1 1 6 6 d2 d1 5 2 3 4 solder mask (hatch area) notes: 1. a pin 1 identifer must be located in the index area indicated. the pin 1 identifer can be: a molded mark/identifer; an embedded metal marker; or a printed indicator. supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such appl ications unless it receives an adequate ?product liability indemnification insurance agreement.? supertex inc. does not assume responsibility for use of devices described, and limits its liabilit y to the replacement of the devices determined defective due to workmanship. no responsibility is assumed for possible omissions and inaccuracies. circuitry and specifications are subject to change without notice. for the latest product specifications refer to the supertex inc. (website: http//www .supertex.com) ?2014 supertex inc. all rights reserved. unauthorized use or reproduction is prohibited. supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.co m LN100 doc.# dsfp-LN100 a031414
|
